The present invention is related in general to the field of semiconductor devices and processes, and more specifically to integrated circuits that permit wire bonding to be performed directly over portions of the active circuit area.
Two independent trends in semiconductor technology, both with a long history, contribute to the urgency for the present invention. The first trend concerns aspects of manufacturing cost savings by conserving semiconductor xe2x80x9creal estatexe2x80x9d.
In order to accommodate balls of bonding wires or solder, typical bonding pads on silicon integrated circuits ICs) have to be of sufficient size; they typically range from squares of 80xc3x9780 xcexcm to squares of 150xc3x97150 xcexcm. They consume, therefore, an area between approximately 1 and 20% of the circuit area, dependent on the number of bonding pads and the size of the integrated circuit. For manufacturing and assembly reasons, the bonding pads are arranged in rows along the periphery of the circuit, usually stringed along all four chip sides.
Until now, all semiconductor devices manufactured had to exclude the area covered by the bonding pads from use for laying out actual circuit patterns because of the high risk of damaging the circuit structures due to the unavoidable forces needed in the bonding process. Evidently, considerable savings of silicon real estate can be obtained if circuit patterns could be allowed to be laid out under the bonding pad metal. One way to achieve this would be to create another level of metallization dedicated solely to bonding pad formation. This level would be built over a protective overcoat covering an active circuit area. In existing technology, however, a special stress buffer layer of polyimide has to be applied between the protective overcoat and the extra metal layer, as shown by K. G. Heinen et al. (xe2x80x9cWire Bonds over Active Circuitsxe2x80x9d, Proc. IEEE 44th Elect. Comp. Tech. Conf., 1994, pp. 922-928). The cost of applying this polyimide layer has so far prohibited the implementation of the bonds-over-active-circuit concept.
Another approach in existing technology has been proposed in U.S. Patent Application No. 60/092,961, filed Jul. 14, 1998 (Saran, xe2x80x9cSystem and Method for Bonding Over Active Integrated Circuitsxe2x80x9d). In order to make the bonding pads strong enough to withstand the mechanical forces required in the wire bonding process, reinforcing systems under the bonding pad are described which utilize specific portions of the actual IC as the means to reinforce weak dielectric layers under the bonding pad. This method requires specific design or redesign of the IC and is poorly suited for standard linear and logic ICs which often have numerous bonding pads but relatively small circuit areas.
The second trend concerns certain processes in the assembly of a semiconductor chip. It is well known that bonding pads in silicon ICs can be damaged during wafer probing using fine-tip tungsten needles, further during conventional thermosonic wire bonding to aluminum metallization on the circuits, or during solder ball attachment in chip-to-substrate devices of more recent assembly developments. In wire bonding, particularly suspect are the mechanical loading and ultrasonic stresses applied the tip of the bonding capillary to the bonding pad. When the damage is not apparent during the bonding process, the defects may manifest themselves subsequently by succumbing to thermo-mechanical stresses generated during the plastic encapsulation, accelerated reliability testing, temperature cycling, and device operation. The damage appears in most cases as microcracks which may progress to fatal fractures in the underlying dielectric material, as chip-outs of brittle or mechanically weak dielectric films, often together with pieces of metal or silicon, or as lifted ball bonds, or as delamination of metal layers.
Recent technological developments in the semiconductor technology tend to aggravate the problem. For instance, newer dielectric materials such as silicon-containing hydrogen silsesquioxane (HSQ) are being preferred due to their lower dielectric constant which helps to reduce the capacitance C in the RC time constant and thus allows higher circuit speeds. Since lower density and porosity of dielectric films reduce the dielectric constant, films with these characteristics are introduced even when they are mechanically weaker. Films made of aerogels, organic polyimides, and parylenes fall into the same category. These materials are mechanically weaker than previous standard insulators such as the plasma-enhanced chemical vapor deposited dielectrics. Since these materials are also used under the bonding pad metal, they magnify the risk of device failure by cracking.
In addition, the spacing between bonding pads is being progressively reduced to save valuable silicon real estate. Consequently, the bonding parameters have to become more aggressive to achieve stronger bonds in spite of the smaller size. Bonding force and ultrasonic energy during bonding are being increased. Again, the risk of yield loss and lowered reliability is becoming greater.
For conventional bonding pad metallization processes, a solution to the aforementioned problems was disclosed in U.S. patent application Ser. No. 08/847,239, filed May 1, 1997 (Saran et al., xe2x80x9cSystem and Method for Reinforcing a Bond Padxe2x80x9d). Some concepts and methods of this disclosure have been subsequently described by M. Saran et al. in a publication entitled xe2x80x9cElimination of Bond-pad Damage through Structural Reinforcement of Intermetal Dielectricsxe2x80x9d (Internat. Reliab. Physics Symp., March 1998). In essence, a metal structure designed for mechanical strength serves as a reinforcement for the mechanically weak dielectric layer. The metal is deposited and then etched to form xe2x80x9creservoirsxe2x80x9d to be filled with the dielectric material, for example HSQ. Since HSQ is deposited by a spin-on process, the sizes of the reservoirs have to remain large enough to be filled controllably with the dielectric. This requirement is contrary to the industry trend for continued shrinking of all circuit feature sizes.
When the insulator film is formed first, openings such as trenches are etched into this film; metal such as copper or aluminum is then deposited to fill these openings, while metal deposited elsewhere on the surface is removed grinding and polishing (so-called damascene metallization process). Wire bonding and solder ball flip-chip bonding over damascene metal pads are facing the same risks of cracking weak dielectric layers as in the case of conventional metallization. U.S. Patent Application No. 60/085,876, filed May 18, 1998 (Saran et al., xe2x80x9cFine Pitch System and Method for Reinforcing Bond Pads in Semiconductor Devicesxe2x80x9d) teaches the design and fabrication process for metal structures made with the damascene technique reinforcing weak dielectrics under the bonding pads.
An urgent need has therefore arisen for a low-cost, reliable mass production system and method providing the manufacture of wire and solder ball bonds directly over active IC areas. The system should provide stress-free, simple, and no-cost-added contact pads for flexible, tolerant bonding processes even when the contact pads are situated above one or more structurally and mechanically weak dielectric layers. The system and method should be applicable to a wide spectrum of design, material and process variations, leading to significant savings of silicon, as well as to improved process yield and device reliability. Preferably, these innovations should be accomplished using the installed process and equipment base so that no investment in new manufacturing machines is needed.
According to the present invention for semiconductor integrated circuits (ICs), at least a portion of a contact pad can be positioned over the IC, when a combination of a bondable metal layer, a stress-absorbing metal layer, and a mechanically strengthened, electrically insulating layer, separate the contact pad and the portion of the IC, provided that each layer has sufficient thickness. This combination of layers and thicknesses provides a system strong enough to withstand the mechanical forces required in the bonding process.
The present invention is related to high density ICs, especially those having high numbers of metallized inputs/outputs, or contact pads. These circuits can be found in many semiconductor device families such as standard linear and logic products, processors, digital and analog devices, high frequency and high power devices, and both large and small area chip categories. The invention saves significant amounts of silicon real estate and thus permits the shrinking of IC chips. Consequently, the invention helps to alleviate the space constraints of continually shrinking applications such as cellular communications, pagers, hard disk drives, laptop computers and medical instrumentation.
The invention utilizes the materials and the sequence of processing steps applied to producing the IC. The metals and dielectric offering high stress-absorbing characteristics are applied as layers of sufficient thickness. No extra layers of stress-absorbing materials such as polyimides are needed.
It is an object of the present invention to reduce the cost of IC chips by reducing the silicon area consumed for the overall circuit design. This object is achieved through utilizing the areas underneath the (numerous) contact pads by positioning portions of the actual circuit under the bond pad areas while simultaneously exploiting the metal and insulating layers separating the contact pad and the circuit portions for functions in the circuit design.
Another object of the present invention is to advance the process and operation reliability of semiconductor probing, and wire bonded and solder-attached assemblies by providing the metal and insulating layers separating the contact pad and the circuit portions in thicknesses sufficient to reliably absorb mechanical, thermal and impact stresses.
Another object of the invention is to eliminate restrictions on the processes of probing and of wire bonding and solder attachment, thus minimizing the risks of inflicting cracking damage even to very brittle circuit dielectrics.
Another object of the invention is to provide design and layout concepts and process methods which are flexible so that they can be applied to many families of semiconductor IC products, and are general, so that they can be applied to several generations of products.
Another object of the invention is to provide a low-cost and high-speed process for fabrication, testing and assembly.
Another object of the invention is to use only design and processes most commonly used and accepted in the fabrication of IC devices, thus avoiding the cost of new capital investment and using the installed fabrication equipment base.
These objects have been achieved by the teachings of the invention concerning design concepts and process flow suitable for mass production. Various modifications have been successfully employed so satisfy different selections of product geometries and materials.
In one embodiment of the invention, at least one portion of the IC is disposed under the contact pad, occupying a substantial area under the contact pad. This concept is applied to circuit designs employing two or more levels of metal. In this embodiment, the layer of bondable metal is preferably copper-doped aluminum about 1400 nm thick; the stress-absorbing metal is preferably titanium-tungsten alloy about 300 nm thick; and the mechanically strengthened, electrically insulating layer is preferably silicon nitride about 1000 nm thick. For the layer of bondable metal, aluminum can be substituted by copper, preferably about 1500 nm thick. Examples for suitable circuit portions under the contact pad include resistors, interconnectors, electrostatic discharge structures, inductors, and capacitors. In addition, transistors (preferably CMOS transistors) may be placed under the contact pad.
In another embodiment of the invention, the electrically insulating layer further serves as the protective overcoat of the IC, since it is made of moisture-impenetrable silicon nitride. In addition, the bondable metal layer and the stress-absorbing metal layer further serve as the metallization of the contact pad. The thicknesses of the combination of layers are optimized for the thermal, impact and ultrasonic stresses encountered in wire ball bonding.
In another embodiment of the invention, the bondable metal layer is further modified to include an interface metal layer of, for example, nickel, and a solderable metal layer of, for example gold, palladium or platinum. The thicknesses of the combination of layers are optimized for the reflow stresses encountered in solder attachment.
In another embodiment of the invention, the relative positions of the via, connecting the contact pad and the circuit, and the bonding wire ball are varied in order to ascertain the insensitivity of the system and the process with respect to the stresses associated with the different positions.
The technical advances represented by the invention, as well as the objects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.